I believe being an engineer is more of a state of mind than an actual profession. I strongly believe than anyone that enjoys fixing things and problem solving can and should be an engineer.

Full resume (pdf)

Born in Cannes, France in 1978. Received Msc. from ESIEE " École Supérieure d'Ingénieurs en Électronique et Électrotechnique" in Paris, France. After graduation in 2001, joined Fujitsu Processor Technology (FPT) for a research and development position on SPARC micro- processors in San Jose, California.

Then, he decided to joined ACSEL under Prof. V. G. Oklobdzija to pursue a Ph.D. for more in depth research.

• Ultra low power design
• High-speed and low power clocked storage elements
• Arithmetic and clocking in VLSI design.

1. Optimal Inductance Management (for on-chip Active Power Supply)
2. Four-state switched decoupling capacitor system for APS
3. Complement reset buffer
4. Complement reset latch
5. Complement reset multiplexer latch

• "Logic Style Comparison for Ultra Low Power Applications", C. Giacomotto, V.G. Oklobdzija, Techcon 2005 (Semiconductor Research Corp.), Oct.24-26
• "Energy-Delay Space Analysis for Clocked Storage Elements under Process Variations", C. Giacomotto, N. Nedovic, V. G. Oklobdzija, 16th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Montpellier, France Sept. 13-15, 2006.
• "The Effect of the System Specification to the Optimal Choice of Clocked Storage Elements", N. Nedovic, C. Giacomotto, V.G. Oklobdzija, Journal of Solid State Circuits, in press 2007